ADVC MICRO 2026

MICRO 2026 Workshop

ADVC 2026

1st Workshop on Agile Development and Verification for Chips

A focused forum on agile chip development, rigorous verification, and the tools that make both possible.

View the call for papers Explore the workshop
Date
October 31, 2026
Location
Athens, Greece
Presented at
MICRO 2026

Chip design is changing.
Verification must keep up.

Agile development and verification for reliable chips.

AI applications, particularly large language models and AI agents, are creating increasingly complex, diverse, and rapidly evolving computing demands. Specialized chips are becoming increasingly important, yet the high costs of conventional design tools, engineering effort, and IP, combined with long design cycles, make it difficult to keep pace with these changing demands.

The hardware community is responding by embracing agile development and verification methodologies. Open, community-driven projects such as XiangShan have demonstrated the potential of this approach through production silicon and adoption by multiple companies. Meanwhile, a growing ecosystem of tools and infrastructure is enabling efficient functional verification and rapid performance exploration.

The central challenge is soundness: agile verification must match the rigor of traditional methods while reducing human effort and verification time. LLMs and agents may further revolutionize chip design and verification, potentially enabling workflows with little or no human intervention.

ADVC invites experts from academia and industry to share experience and vision, welcoming traditional approaches such as formal verification and fuzzing alongside emerging AI-driven methods.

Call for Papers

Topics of Interest

We invite papers on agile development and verification for chips. Submissions may present mature research, work in progress, industrial experience, or new directions for the community.

  • Agile chip development and verification methods, including reusable tools, infrastructure, and experience from practice
  • Rapid design-space exploration and rigorous verification, including
    • Agile microarchitectural exploration and PPA optimization
    • Rapid compiler-hardware co-design and optimization
    • Automated architectural security analysis and verification
    • Scalable and efficient verification methodologies
  • Agile hardware development tools, infrastructure, or workflows for
    • Functional and performance verification
    • Rapid performance exploration and evaluation
    • Adoption of AI and AI agents in hardware development
    • Acceleration of RTL simulation
    • AI-native hardware programming languages

Paper Submission

Submissions may present a research result, a position or systems paper, an industrial experience report, or a demonstration of a verification tool, infrastructure, or open-source project.

We welcome the following forms of contribution:

  • Research papers: completed research with a clear problem, method, experimental evaluation, and conclusions.
  • Position papers: perspectives on agile development or verification, including challenges, roadmaps, and open questions.
  • Systems papers: working toolchains, platforms, infrastructure, or end-to-end systems, supported by evidence from use or evaluation.
  • Industrial experience reports: workflows, scale, metrics, lessons learned, failures, and transferable insights from real projects.
  • Demonstrations: live presentations of tools, infrastructure, or open-source projects, describing the demonstration, its dependencies, and availability.
Submit

Important dates

Submission deadlineSeptember 21, 226
NotificationSeptember 28, 2026 (before early registration)
WorkshopOctober 31, 2026 · 8:00 AM - 12:00 PM

Organizers